1. Field of the Invention
This invention relates generally to electronic circuits, and in particular to silicon controlled rectifier (SCR) structures for electrostatic discharge protection (ESD). More particularly this invention relates to polycrystalline silicon (polysilicon) bounded SCR structures and to electronic protection circuits employing polycrystalline silicon bounded SCR's.
2. Description of Related Art
In ESD protection circuits, the series resistance of the active devices affects the performance of the devices. Higher resistance at the voltage levels of an ESD event may lead to a voltage drop across the active devices that may destroy the device. FIG. 1 shows an ESD protection diode structure of the prior art. In this example, shallow trenches are etched within the region that will become the N-well 10 and filled with an insulating material to form the shallow trench isolation (STI) 15 are formed on the substrate. A semiconductor material that is lightly doped with a p-type impurity is formed on the substrate to construct the P-well 5. Within the P-well 5, a lightly doped n-type impurity is diffused into the P-well 5 to form the N-well 10. Between two of the STI regions 15 a P-type material is diffused into the N-well until a heavily doped P+ region 20 is formed. Similarly, between two other STI regions 15 an N-type material is diffused into the N-well until a heavily doped N+ region 25 is formed. An insulative layer 40 is formed on the surface of the substrate and opening 32 and 37 are created over the P+ region 20 and the N+ region 25. Silicides 30 and 35 are respectively formed on the surfaces of the P+ region 20 and N+ region 25 to create the necessary contacts to external circuitry. In the case of the ESD protection diodes shown, the contacts will be to the signal input/output interface connection pads and the power supply voltage source connection pads.
According to U.S. Pat. No. 5,629,544 (Voldman, et al.—544), diode series resistance is largely determined by the dimensions of the diode features, the resistivity of N-well 10 in which diode is located, the distance current flows in N-well 10 and the depth of the current path, and by the resistance of contacts 30 and 35 to the p+ and n+ diffusions 20 and 25. Thus, a wider diode with a lower well resistivity, a shorter current path, and silicided films and contacts provide a lower diode series resistance. In the case of the diode as shown, the depth of the current path is determined by the depth of the STI regions 15. Further, it is known in the art that the width of the STI regions 15 have certain achievable minimums that cause the series resistance to be larger than desired.
Voldman, et al.—544 and “Semiconductor Process and Structural Optimization of Shallow Trench Isolation-Defined And Polysilicon-Bound Source/Drain Diodes For ESD Networks,” Voldman, et al., Proceedings Electrical Overstress/Electrostatic Discharge Symposium, October 1998, pp: 151-160 discusses polysilicon-bounded diode. Refer to FIG. 2 for more discussion of the structure of a polysilicon bounded diode. The structure of the polysilicon bounded diode is constructed in a P-type well 5 that has been created with a substrate has been lightly doped with a p-type impurity. Within the P-well 5 a lightly doped n-type impurity is diffused into the P-well 5 to form the N-well 10. An insulative layer 40 is formed on the surface of the substrate. A gate stack is formed with a gate oxide layer 60 and a polysilicon layer 65. Spacers 70 are added to the sides of the gate oxide layer 60 and the polysilicon layer 65. A P-type material is diffused into the N-well until a heavily doped P+ region 75 is formed and an N-type material is diffused into the N-well until a heavily doped N+ region 80 is formed on each side of the gate stack. Openings 77 and 82 are created over the P+ region 75 and the N+ region 80. Silicides 90 and 95 are respectively formed on the surfaces of the P+ region 75 and N+ region 80 to create the necessary contacts to external circuitry. As described above, the contacts will be to the signal input/output interface connection pads and the power supply voltage source connection pads.
In the polysilicon bounded diode as shown, the gate stack maybe constructed with smaller dimensions than those permitted in the diode constructed with the STI 15 of FIG. 1. This permits the series resistance of the diode to be lower to and thus improves the operation of the diode during an ESD event.
Use of silicon controlled rectifiers (SCR) as ESD protection devices are well known in the art. Referring to FIG. 3, the P-well 100 is constructed of a semiconductor material that is lightly doped with a p-type impurity is diffused into a substrate. Within the P-well 100 a lightly doped n-type impurity is diffused into the P-well 100 to form the N-well 105. Shallow trenches are then etched within the region of the N-well 105 and filled with an insulating material to form the shallow trench isolation (STI) 110. Between two of the STI regions 110 a P-type material is diffused into the N-well until a heavily doped P+ regions 125 and 135 are formed. Similarly, between two other STI regions 110 an N-type material is diffused into the N-well until the heavily doped N+ regions 120 and 130 are formed. An insulative layer 140 is formed on the surface of the substrate and openings 127 and 137 are created over the P+ regions 125 and 135 and openings 122 and 132 are created over the N+ regions 120 and 130. Silicides 145, 150, 155, and 160 are formed on the surfaces of the P+ regions 125 and 135 and N+ regions 120 and 130 to create the necessary contacts to external circuitry. The contacts will be to the signal input/output interface connection pads and the power supply voltage source connection pads.
The SCR is formed of the P+ regions 125, the N-well 105, the P-well 105 and the N+ regions 130. The anode of the SCR being the P+ regions 125 and the cathode N+ regions 130. As structured, a positive voltage of an ESD event applied to the anode will cause the SCR to be activated once the snapback voltage is reached. In general the snapback voltage as shown is greater than 50V and may not cause damage to connected integrated circuits. However, as the feature sizes of integrated circuits have become smaller, the voltages at which damage may occur is becoming smaller and the SCR needs to be triggered at lower voltages that are greater than the operating voltages of the integrated circuits.
“Electrostatic Discharge (ESD) Protection in Silicon-On-Insulator (SOI) CMOS Technology with Aluminum and Copper Interconnects in Advanced Microprocessor Semiconductor Chips,” Voldman, et al., Proceedings Electrical Overstress/Electrostatic Discharge Symposium, 1999, pp: 105-115, discusses the electrostatic discharge (ESD) robustness of silicon-on-insulator (SOI) high-pin-count high-performance semiconductor chips. The ESD results demonstrate that sufficient ESD protection levels are achievable in SOI microprocessors using lateral ESD SOI polysilicon-bound gated diodes.
“An ESD Protection Scheme for Deep Sub-Micron ULSI Circuits,” Sharma, et al. Digest of Technical Papers—1995 Symposium on VLSI Technology, 1995, pp: 85-86, describes a scheme for on-chip protection of sub-micron ULSI circuits against ESD stress using low voltage zener-triggered SCR, and a zener-triggered thin gate oxide MOSFET.
U.S. Pat. No. 6,610,262 (Peng, et al.) describes an ESD semiconductor protection with reduced input capacitance.
U.S. Pat. No. 6,605,493 (Yu) teaches about an SCR ESD protection device used with shallow trench isolation structures. The invention incorporates polysilicon gates bridging SCR diode junction elements and also bridging between SCR elements and neighboring STI structures. The presence of the strategically located polysilicon gates effectively counters the detrimental effects of non-planar STI “pull down” regions as well as compensating for the interaction of suicide structures and the effective junction depth of diode elements bounded by STI elements. Connecting the gates to appropriate voltage sources such as the SCR anode input voltage and the SCR cathode voltage, typically ground, reduces normal operation leakage of the ESD protection device.
U.S. Pat. No. 6,580,184 (Song) illustrates an ESD protection circuit having a silicon-controlled rectifier structure. A switch circuit is connected between a ground voltage terminal and a well region that is a base of the PNP transistor. The switch circuit is formed of plural diode-coupled MOS transistors, so that a trigger voltage of the SCR is determined by threshold voltages of the MOS transistors.
U.S. Pat. No. 6,534,834 (Ashton, et al.) teaches about a snapback device that functions as a semiconductor protection circuit to prevent damage to integrated circuits resulting from events such as electrostatic discharge. The snapback device includes a polysilicon film overlapping the active area.
U.S. Pat. No. 5,453,384 (Chatterjee) describes a silicon controlled rectifier structure that is provided for electrostatic discharge protection. A polysilicon gate layer is formed over a gate insulator region and is electrically coupled to the input pad of an integrated circuit.
U.S. Pat. No. 5,159,518 (Roy) details an input protection circuit that protects MOS semiconductor circuits from electrostatic discharge voltages and from developing circuit latchup. The input protection circuit includes a low resistance input resistor, and two complementary true gated diodes.
U.S. Patent Application 2003/0016479 (Song) describes an ESD protection circuit having silicon-controlled rectifier structure that includes a PNP transistor and an NPN transistor. A switch circuit is connected between a ground voltage terminal and a well region that is a base of the PNP transistor. The switch circuit is formed of plural diode-coupled MOS transistors, so that a trigger voltage of the SCR is determined by threshold voltages of the MOS transistors.